PowerPro is the commercially available RTL sequential power optimization and power analysis tool. As a member of the PowerPro engineering team, you will be responsible for:
• Developing applications to aid towards RTL power optimization
• Driving architecture of new features.
• Good knowledge of C++, STL, Data Structures, Algorithms.
• Minimum 3 years+ experience in EDA/ Software development.
• Understanding of Digital Design using Verilog or VHDL.
• Knowledge of HDL i.e. Verilog, VHDL, SV will be a plus.
• Knowledge of scripting languages like Perl/Tcl/Sed/Awk will be a plus.
Job ID: 117563
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Early Professional
Job Type: Full-time