Position – R&D Software Engineer_RTLC
Work Location – Noida
Experience – 2 to 4 yrs
Overview - Design verification at RTL level is critical for time to market and various innovative ways are needed for faster verification. Emulation based verification had been grown significantly over years due to increase in design size and various verification complexity in all domain being functional validation, power verification/estimation and most important performance. Extended verification complexity is needed to do shift left in verification area. Performance plays a significant role in emulation based validation to make sure design verification is done in time. Mentor emulation platform Veloce leads solving above challenges in all domains.
The person in this role will be responsible for developing, enhancing and maintaining key technology components of the RTL Compiler (frontend RTL Synthesis for Veloce) of Mentor Graphics in verification domain.
The candidate should have experience in EDA software, preferably in the RTL synthesis domain. Develop key software components with high quality results on RTL synthesis.
Work on various RTL Synthesis optimizations as wells as on technology mapping flow
Independently test, benchmark and fix issues in synthesis.
Identify and work on potential improvements and optimizations.
Extend and maintain the functionality of the RTL Compiler as needed.
Write technical specs and participate in technical discussions, code reviews.
Work with the team to jointly solve technical problems and within given deadline
Job ID: 119474
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Experienced Professional
Job Type: Full-time