R&D Software Engineer (C,C++, VHDL, Verilog) SISW-Mentor 184011

Job Description

Company: SISW - Mentor
Job Title:   R&D Software Engineer (C,C++, VHDL, Verilog) - 184011
Job Location: USA - CA - Fremont
Job Category: R&D/Software Engineering


Position Overview:

We have a creative, dynamic and highly productive small team environment and are looking for motivated, highly capable contributors to help develop advanced functional verification tools.

Your work will including developing and applying formal analysis and static verification techniques to different parts of the ASIC and FPGA design methodologies. You must understand how to apply netlist creation, traversal, analysis, simulation and formal technologies to solve problems.


Job Qualifications:

- PhD or Master and 3+ years or Bachelors and 6+ years of experience in EDA

- Expertise in the design of model checking algorithms and the application of formal verification methods

- Previous experience in building RTL synthesis or simulation products.

- Knowledge of Verilog, VHDL, System Verilog

- Strong knowledge of programming languages (C/C++, Boost, STL)

- Solid software engineering skills and discipline are required

- Knowledge of PSL or SVA assertion languages is a plus



Job ID: 184011

Organization: Digital Industries

Company: Mentor Graphics Corporation

Experience Level: Experienced Professional

Job Type: Full-time

Equal Employment Opportunity Statement
Siemens is an Equal Opportunity and Affirmative Action Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to their race, color, creed, religion, national origin, citizenship status, ancestry, sex, age, physical or mental disability, marital status, family responsibilities, pregnancy, genetic information, sexual orientation, gender expression, gender identity, transgender, sex stereotyping, protected veteran or military status, and other categories protected by federal, state or local law.

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