R&D SW Engineer (RTLC)_SMTS_54195

Job Description

Design verification at RTL level is critical for time to market and various innovative ways are needed for faster verification.

Hardware assisted (Emulation/Prototype) based verification had been grown significantly over years due to increase in design size and various verification complexity in all domain being functional validation, power verification/estimation and most important performance. Extended verification complexity is needed to do shift left in verification area.

Mentor emulation platform Veloce leads solving above challenges in all domains and RTLC is synthesis compiler of Veloce and Veloce-Primo. Good quality of synthesis result is key for RTLC. This applies to both capacity as well as model performance.

Roles & responsibilities

  • The person in this role will be responsible for designing high level synthesis optimizations done especially at synthesis backend stage inclusive of understanding of new target technology and support this.
  • Job demands handling of above responsibility.

Skills required

  • 2 + year of experience in RTL synthesis domain with expertise synthesis optimizations especially at netlist level.
  • Strong software background with good s/w designing skills are extremely important.
  • Person must be well verse with HDL languages (Verilog/ VHDL/SV/..) and various verification features. 
  • LI-MGRP

Job ID: 189189

Organization: Digital Industries

Company: Mentor Graphics (India) Private Limited

Experience Level: Experienced Professional

Job Type: Full-time

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