R&D SW Engineer _RTLC
Experience – 4 -12 years
- Design verification at RTL level is critical for time to market and various innovative ways are needed for faster verification.
- FPGA based prototype flow is one important piece of this puzzle.
- This job needs to lead motivated team to deliver front end synthesis compiler for FPGA based prototype verification platform.
- Person should be verbose with s/w programming on C/C++ with good understanding of Data Structures and Algorithms.
- Knowledge of HDL (hardware descriptive languages like Verilog/VHDL/System Verilog) for synthesis perspective will be needed along with high level understanding of digital electronics.
Job ID: 193833
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Experienced Professional
Job Type: Full-time