Emulation Verification Engineer-SISW-Mentor

Job Description

Job Description - VTL Verification
• Development of verification environments for emulation on standard protocol
• Suggest and prototype various verifications flows using Veloce
• Integration and qualification of various supported solutions like Questa, zero-in, codelink (Mentor Graphics provided
• Integration and qualification of various vertical solutions available with us e.g. various internal IP cores, hardware
solutions with developed design
• Protocol / Practical experience on any of the following protocol is necessary –
• 3-8 years of experience
• Experience in IP and SOC level verification using SV/UVM
• Added advantage if person knows c/c++/system c
• Knowledge of verification methodologies like UVM, OVM, TLM, Assertion, Coverage, co-simulation, co-verification
• Good communication skills as person needs to work with external interfaces
• FPGA synthesis knowledge and emulation experience is high positive
• Good scripting and automation knowledge is big plus for the role

• B.Tech/M.Tech from a reputed institute


Job ID: 194479

Organization: Digital Industries

Company: Mentor Graphics (India) Private Limited

Experience Level: Experienced Professional

Job Type: Full-time

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