Mentor, a Siemens Business is looking for a highly motivated design engineer to join the R&D team developing Design-forTest tools as part of the Tessent product line. The candidate would join the leading-edge team responsible for the development of the IEEE1149.10 product where highspeed SERDES lanes are used to carry test data in and out of the chip.
The responsibility involves:
the design and implementation of the Verilog RTL IP with complete flow automation within the chip design process
integration between IEEE1149.10 with the ATPG and IJTAG components of the Tessent Shell platform is important aspect of the job
several programing languages including Verilog, TCL, C++ and several design automation tools proprietary languages are used
The successful candidates must possess the following combination of education and experience:
BS/MS/Ph.D. in Computer Science, Electrical or Computer Engineering, or other related field.
1+ years (including one year in commercial environment) of software engineering experience in C++.
Working knowledge of Linux and one or more scripting languages.
Knowledge of digital logic design along with hardware description languages, such as Verilog or VHDL.
Strong analysis, design, and problem-solving skills.
Attention to details and the ability to accurately estimate software and hardware tasks and delivery on schedule.
Good verbal, written, and interpersonal communication skills in English
Good background of DFT and best-known industry practices.
Knowledge and experience in all aspects of design flows – such as test, synthesis, simulation, formal verification, timing optimization, and other related design tasks.
Organization: Digital Industries
Company: Mentor Graphics Polska Sp. z o.o.
Experience Level: Experienced Professional
Job Type: Full-time