- Maintaining a deep knowledge of High Level Synthesis with focus on Front End Design & technology
- Develop, test, maintain and improve HLS based designs & methodologies
- ASIC/FPGA design flow knowledge, to assist efficiently with further deployment of the technology
- Being recognized as a go-to-person for Mentor’s C2GDS products. Playing a critical role in driving business by addressing & supporting customers.
- Gathering customer requirements to provide a clear view to the division to help shape product development
- Working in different design
- A minimum of Bachelors in EC, EE, CS from a reputed university.
- 2-8 years of industry experience or EDA primarily in Front End ASIC/FPGA flows.
- Requires a strong understanding of Digital Implementation tools/flows.
- A team player with good analytical and debug skills.
- Must be technical expert with hands-on experience with understanding High Level Synthesis, RTL (Verilog /VHDL), physical synthesis, Simulation.
- Programming knowledge of in C/C++ for HLS is required. SystemC is a plus.
- Experience in running, debugging, validating, and profiling programs on HW design is a big advantage.
- Requires prior working experience with one/more of the following tools: Mentor (Catapult-HLS, Vivado HLS, Oasys-RTL, ModelSim), Synopsys (Design Compiler (DCT/DCG)),Cadence(Stratus,RC,NCSIM).
- Must have basic experience in of the scripting language like shell script, perl or python.
- Customer sensitivity, the ability to multiplex many issues and the desire to assist customers exploit new technologies are essential for success in the position
- A person with a go-getter attitude , aggressive stance, good problem-solving, inter-personal, oral and written communication skills
- Must be able to travel for short-medium terms to worldwide locations.
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Experienced Professional
Job Type: Full-time