Engineer will be responsible for design, characterization and verification of memory compilers for functionality, robustness and electrical integrity.
· Assisting the design team with extensive electrical margin simulations to cover all features and configurations supported by the memory compiler. He/she will need to ensure all memory cuts/configurations meet the design specs and has the ability to analyze spice simulation failures and isolate problematic circuits in order to provide feedback to design team for circuit updates.
· Conducting verification on the various Front-End views (lef, mbist, atpg, lib, Verilog) and Back-End Views (cdl, GDSII) provided by the memory compiler. He/she will need to be able to debug verification failures and isolate root cause for failures in the models.
· Create compiler timing/power estimators for model generation. This will involve gathering large amount of timing/power data from spice simulations of critical memory cuts to create multi-variable equations through weighted linear regression. Good understanding of timing/power dependencies of various memory parameters will be needed.
Bachelor required/Masters preferred in Electrical or Computer Engineering with 3+ years of experience
· Good knowledge of transistor-level circuits and SRAM design
· Good understanding of memory architecture and correlation of memory PPA to different memory parameters
· Experience with scripting languages – perl
· Understands various flows and methodologies, including : functional verification, static timing analysis, spice simulation and analysis, IR and EM analysis
· Good knowledge of memory front-end viewsand associated verification flow (e.g. Verilog/BIST/Liberty/ATPG models)
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Experienced Professional
Job Type: Full-time