Senior Applications Engineer (QVIP, functional verification) - SISW - MG 199247

Job Description

Company:  SISW - MG       
Job Title:    Senior Applications Engineer (QVIP, functional verification) - 199247
Job Location: USA - CA - Fremont
Job Category: Applications Engineer



Job Description:

Support the use of Mentor’s Verification IP (QVIP) technologies in design and verification of complex SoC chips for the world's largest electronics and semiconductor IC companies. This position brings the technical role to the Americas' Account team, based in Fremont, CA. As a Functional Verification Application Engineer, you will be part of a team comprising of
Account Manager, Account Technology Manager, Product Engineer, Product Specialists, contributing to increase the deployment and adoption of Functional Verification products within North America customers, and develop new customers.

The Functional Verification Applications Engineer will be responsible for:

• Providing technical leadership for all QVIP protocols and solutions, contribute toward and execute on pre/post sales strategy established by the regional account team.
• Uncovering, Qualifying and Executing opportunities in the regional territory.
• Articulating customer’s technical requirements and Influencing product engineering to shape product direction.
• Developing technical presentations, conducting demonstrations, evaluations, and benchmarks.
• Effectively communicating how Mentor's solutions will solve customer’s problems.
• Building and maintaining ongoing positive relationships with customers.
• Working collaboratively with Product Engineers and R&D engineering team members to ensure mutual success and QVIP business growth.


Job Qualifications:

The successful candidate will possess the following combination of education and experience:
• BSEE, BSCS or related engineering discipline plus min 5 years of experience in the EDA, or Semiconductor field related with IP protocols.
• MSEE, MSCS or related engineering discipline plus min 3 years of experience in EDA, or Semiconductor field related with IP protocols.
• A strong understanding of Design and Verification concepts in ASIC & FPGA flow is required.
• Knowledge of Advanced Verification methodologies & environments, commonly used protocols like ETH, PCIE, DDR, USB, AMBA, other is essential.
• Expert in coding with Verilog/VHDL/System Verilog, UVM, SVA is highly desired.
• Experience with Simulation, Debugging, Formal & Emulation technology is a plus.
• Good presentation and communication skills are essential.
• Self-motivated and self-disciplined.


#LI-MGRP

Organization: Digital Industries

Company: Mentor Graphics Corporation

Experience Level: Experienced Professional

Job Type: Full-time



Equal Employment Opportunity Statement
Siemens is an Equal Opportunity and Affirmative Action Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to their race, color, creed, religion, national origin, citizenship status, ancestry, sex, age, physical or mental disability, marital status, family responsibilities, pregnancy, genetic information, sexual orientation, gender expression, gender identity, transgender, sex stereotyping, protected veteran or military status, and other categories protected by federal, state or local law.

EEO is the Law
Applicants and employees are protected under Federal law from discrimination. To learn more, Click here.

Pay Transparency Non-Discrimination Provision
Siemens follows Executive Order 11246, including the Pay Transparency Nondiscrimination Provision. To learn more, Click here.

California Privacy Notice
California residents have the right to receive additional notices about their personal information. To learn more, click here.

Can't find what you are looking for?

Let's stay connected

Can't find what you are looking for?